--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data eq
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ  VERSION_END


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--synthesis_resources = lut 4 
SUBDESIGN decode_f8a
( 
	data[1..0]	:	input;
	eq[3..0]	:	output;
) 
VARIABLE 
	data_wire[1..0]	: WIRE;
	eq_node[3..0]	: WIRE;
	eq_wire[3..0]	: WIRE;
	w_anode338w[2..0]	: WIRE;
	w_anode352w[2..0]	: WIRE;
	w_anode361w[2..0]	: WIRE;
	w_anode370w[2..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	eq[] = eq_node[];
	eq_node[3..0] = eq_wire[3..0];
	eq_wire[] = ( w_anode370w[2..2], w_anode361w[2..2], w_anode352w[2..2], w_anode338w[2..2]);
	w_anode338w[] = ( (w_anode338w[1..1] & (! data_wire[1..1])), (w_anode338w[0..0] & (! data_wire[0..0])), B"1");
	w_anode352w[] = ( (w_anode352w[1..1] & (! data_wire[1..1])), (w_anode352w[0..0] & data_wire[0..0]), B"1");
	w_anode361w[] = ( (w_anode361w[1..1] & data_wire[1..1]), (w_anode361w[0..0] & (! data_wire[0..0])), B"1");
	w_anode370w[] = ( (w_anode370w[1..1] & data_wire[1..1]), (w_anode370w[0..0] & data_wire[0..0]), B"1");
END;
--VALID FILE
